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MT-023 tutorial adc architectures iv: sigma-delta adc advanced concepts and applications by walt kester introduction tutorial mt-022 discussed the basics of - adcs. in this tutorial, we will look at some of the more advanced concepts including idle tones, multi-bit - , mash, bandpass - , as well as some example applications. idle tone considerations in our discussion of - adcs up to this point, we have made the assumption that the quantization noise produced by the - modulator (see figure 1) is random and uncorrelated with the input signal. unfortunately, this is not entirely the case, especially for the first-order modulator. consider the case wher e we are averaging 16 samples of the modulator output in a 4- bit - adc. + _ +v ref ?v ref digital filter and decimator + _ clock kf s v in n-bits f s f s a b 1-bit data stream 1-bit dac latched comparator (1-bit adc) 1-bit, k f s sigma-delta modulator integrator figure 1: first-or der sigma-delta adc figure 2 shows the bit pattern for two input sign al conditions: an input signal having the value 8/16, and an input signal having the value 9/16. in the case of the 9/16 signal, the modulator output bit pattern has an extra "1" every 16th output. this will produce energy at kf s /16, which translates into an unwanted tone. if the oversam pling ratio (k) is less than 8, this tone will fall rev.a, 10/08, wk page 1 of 11
MT-023 into the passband. in audio, the idle tones can be heard just above the noise floor as the input changes from negative to positive fullscale. figure 2: repetitive bit pattern in sigma-delta modulator output figure 3 shows the correlated idling pattern behavior for a first order - modulator, and figure 4 shows the relatively uncorrela ted pattern for a second-order modulator. for this reason, virtually all - adcs contain at least a second-order modulator loop, and some use up to fifth- order loops. figure 3: idling patterns for first-order sigma-delta modulator (integrator output) page 2 of 11
MT-023 figure 4: idling patterns for sec ond-order sigma-delta modulator (integrator output) higher order loop considerations in order to achieve wide dynamic range, - modulator loops greater than second-order are necessary, but present real design challenges. first of all, the si mple linear models previously discussed are no longer fully a ccurate. loops of order greater than two are generally not guaranteed to be stable under all input conditions. the instability arises because the comparator is a nonlinear element whose eff ective "gain" varies inversely with the input level. this mechanism for instability causes the following beha vior: if the loop is operating normally, and a large signal is applied to the input that overloads the loop, the average gain of the comparator is reduced. the reduction in comparator gain in the linear model causes loop instability. this causes instability even when the signal that caused it is removed. in actual practice, such a circui t would normally oscillate on pow er-up due to in itial conditions caused by turn-on transients. the ad1879 dual audio adc released in 1994 by analog devices used a 5 th order loop. extensive nonlin ear stabilization techniques we re required in this and similar higher-order loop designs (references 1-5). multi-bit sigma-delta converters so far we have considered only - converters which contain a single-bit adc (comparator) and a single-bit dac (switch). the block diagram of figure 5 shows a multi-bit - adc which uses an n-bit flash adc and an n-bit dac. o bviously, this architecture will give a higher dynamic range for a given oversampling ratio and or der of loop filter. stab ilization is easier, since second-order loops can generally be used. idling patterns tend to be more random thereby minimizing tonal effects. page 3 of 11
MT-023 digital filter and decimator + _ clock kf s v in n-bits f s f s n-bit data stream n-bits, kf s integrator flash adc n-bits n-bit dac figure 5: multi-bi t sigma-delta adc the real disadvantage of this technique is that the linearity depends on the dac linearity, and thin film laser trimming is required to approa ch 16-bit performance levels. this makes the multi-bit architecture extremely impractical to implement on mixed-signal ics using traditional binary dac techniques. however, fully decoded thermometer dacs (see tutorial mt-014 ) coupled with proprietary data scrambling techniques as used in a num ber of analog devices' audio adcs and dacs, including the 24-bit stereo ad1871 (see references 6 and 7) can achieve high snr and low distortion using the multi-bit architecture. the multi-bit data scrambling technique both minimizes idle tones and ensures better different ial linearity. a simplified block diagram of the ad1871 adc is shown in figure 6. figure 6: ad1871 24-bit 96-ksps stereo audi o multi-bit sigma-delta adc page 4 of 11
MT-023 the ad1871's analog - modulator section comprises a se cond order multi-bit implementation using analog device's proprietary technology for be st performance. as shown in figure 7, the two analog integrator blocks are followed by a flash adc section that generates the multi-bit samples. the output of the flash adc, which is thermometer encoded, is decoded to binary for output to the filter sections and is scramb led for feedback to the two integrator stages. the modulator is optimized for operation at a sampling rate of 6.144 mhz (which is 128 f s at 48-khz sampling and 64 f s at 96-khz sampling). the a-weighted dyna mic range of the ad1871 is typically 105 db. figure 7: details of the ad 1871 second-order modulator and data scrambler digital filter implications on multiplexed applications the digital filter is an integral part of all - adcs?there is no way to remove it. the settling time of this filter affects certain applications especially when using - adcs in multiplexed applications. the output of a multiplexer can present a step function input to an adc if there are different input voltages on adjacent channels. in fact, the multiplexer output can represent a full- scale step voltage to the - adc when channels are switched. adequate filter settling time must be allowed, therefore, in such applications. this does not mean that - adcs shouldn't be used in multiplexed applications, just that the settling time of the digital filter must be considered. some newer - adcs such are actually op timized for use in multiplexed applications. for example, the group delay through the ad1871 di gital filter is 910 s (sampling at 48 ksps) and 460 s (sampling at 96 ksps)?this represents the time it takes for a step function input to propagate through one-half the number of taps in the digital filter. th e total settling time is therefore approximately twice the group delay time. the input oversampling frequency is 6.144 msps for both conditions. the frequency response of the digital filter in the ad1871 adc is shown in figure 8. this filter uses a finite impulse response (fir) design, and therefore has linear phase over the audio passband. duplicating th is performance using an analog filter would require considerable design effort as well as rather costly components. page 5 of 11
MT-023 figure 8: ad1871 24-bit, 96-ksps stereo sigma-delta adc digital filter characteristics in other applications, such as low fr equency, high resolution 24-bit measurement - adcs (such as the ad77xx-series), other types of dig ital filters may be used. for instance, the sinc 3 response is popular because it ha s zeros at multiples of the th roughput rate. a 10-hz throughput rate produces zeros at 50 hz and 60 hz which aids in ac power line rejection. regardless of the type of digital filter, - adcs require that sufficient settling time is allowed after the applica tion of a step function input. multistage noise shaping (mas h) sigma-delta converters as has been discussed, non linear stabilization techni ques can be difficult for 3 rd order loops or higher. in many cases, the multi-bit architecture is preferable. an alternative approach to either of these, called multistage noise shaping (mash), utilizes cascaded stable first-order loops (see references 8 and 9). figure 9 shows a block di agram of a three-stage mash adc. the output of the first integrator is subtra cted from the first dac output to yield the first stage quantization noise, q1. q1 is then quantized by the second stage. the output of the second integrator is subtracted from the second dac out put to yield the second stage qua ntization noise which is in turn quantized by the third stage. the output of the first stage is summed with a single digital differentiation of the second stage output and a double different iation of the third stage output to yield the final out put. the result is that the quantization noise q1 is suppressed by the second stage, and the quantization noise q2 is suppressed by the third stage yielding the same suppression as a third-order loop. since this result is obtained using three first- order loops, stable operation is assured. page 6 of 11
MT-023 figure 9: multi-stage noise sh aping sigma-delta adc (mash) high resolution measurement sigma-delta adcs while older integrating architectures such as dua l-slope are still used in digital voltmeters, cmos - adcs are the dominant converter for toda y's industrial measurement applications. these converters offer excellent 50-hz/60-hz power line common-mode rejection and resolutions up to 24 bits with various digital features, such as on-chip calibration. many have programmable gain amplifiers (pgas) which allow the direct digitization of small signals from bridge and thermocouple transducers without the need for additional exte rnal signal conditioning circuits. in order to better unders tand the capability of - measurement adcs and the power of the technique, a modern example, the 24-bit ad7799 , will be examined in detail. the ad7799 is a member of the ad77xx family and is shown in figure 10. this adc was specifically designed to interface directly to low-level sensor outputs su ch as bridges in weigh scale applications. the device accepts low-level signals directly from a bridge and outputs a seri al digital word. there are three multiplexed and buffered differential i nputs which drive an internal instrumentation amplifier. the in-amp can be programmed fo r eight different gains: 1, 2, 4, 8, 16, 32, 64, and 128. page 7 of 11
MT-023 figure 10: ad7799 sigma-delta singl e-supply bridge adc figure 11 shows a direct connect ion between a bridge-based load cell and a high resolution - adc, the ad7799. the fullscale bridge output of 10 mv is digitized to approximately 16 noise- free bits by the adc at a throughput rate of 4.17 hz. ratiometric operation eliminates the need for a precision voltage reference. the ad7799 can be operated at thr oughput rates from 4.17 hz to 500 hz. the part operates with a power suppl y from 2.7 v to 5.25 v and consumes 380 a typical. v exc = +5v v ref = +2.5v ain = 10mv adc 24-bit calibration host system digital ad7799 +5v v dd = +5v force force sense sense in amp figure 11: load cell conditioning usi ng a high resolution sigma-delta adc page 8 of 11
MT-023 bandpass sigma-delta converters the - adcs that we have described so far cont ain integrators, which are low pass filters, whose passband extends from dc. thus, their qua ntization noise is pushed up in frequency. at present, most commercially available - adcs are of this type (although some which are intended for use in audio or telecommunications applications contain bandpass rather than lowpass digital filters to eliminate any system dc offsets). but there is no particular reason why the filters of the - modulator should be lpfs, except th at traditionally adcs have been thought of as being baseband device s, and that integrators are some what easier to construct than bandpass filters. if we re place the integrators in a - adc with bandpass filters (bpfs) as shown in figure 12, the quantization noise is moved up and down in frequency to leave a virtually noise-free region in the pass-band (see re ferences 10, 11, and 12). if the digital filter is then programmed to have its pass-band in this region, we have a - adc with a bandpass, rather than a lowpass characteri stic. such devices would appear to be useful in direct if-to- digital conversion, digital radios, ultrasound, an d other undersampling applications. however, the modulator and the digital bpf must be designed for the specific set of frequencies required by the system application, thereby somewhat limiting the flexibility of this approach. + - + - 1-bit dac analog bpf analog bpf digital bpf and decimator clock kf s f s shaped quantization noise digital bpf response f c f bw f s > 2 bw figure 12: replacing integr ators with resonators gives a bandpass sigma-delta adc in an undersampling application of a bandpass - adc, the minimum sampling frequency must be at least twice the signal bandwidth, bw. the signal is centered aroun d a carrier frequency, f c . a typical digital radio application using a 455- khz center frequency and a signal bandwidth of 10 khz is described in reference 11. an oversampling frequency kf s = 2 msps and an output rate f s = 20 ksps yielded a dynamic range of 70 db within the signal bandwidth. page 9 of 11
MT-023 an early example of a bandpass - adc is the ad9870 if digitizing subsystem having a nominal oversampling frequency of 18 msps, a center frequency of 2.25 mhz, and a bandwidth of 10 khz to 150 khz (see details in reference 12). the ad9874 and ad9864 are general purpose if subsystems that digitize low level 10-300 mhz if signals with bandwidths up to 270 khz (see details in re ference 13). the signal chain contains a low noise amplifier, mixer, bandpass - adc and a decimation filter with programmable decimation factor. an agc circuit pr ovides 12 db of continuous gain adjustment. summary sigma-delta adcs and dacs have proliferated into many modern applications including measurement, voiceband, audio, etc. the technique takes full advantage of low cost cmos processes and therefore makes inte gration with highly digital func tions such as dsps practical. modern techniques such as the multi-bit data scrambled architecture minimize problems with idle tones which plagued early - products. resolutions up to 24-bits are currently available, and the requirements on analog antialiasing/anti-imaging filters are greatly relaxed due to oversampling. the internal digital filter in audio - adcs can be designed for linear phase, which is a major requirement in thos e applications. for high resolution - adcs designed for measurement applications, the digital filter is generally designed so that zeros occur at the mains frequencies of 50 hz and 60 hz. many - converters offer a high level of user program mability with respect to output data rate, digital filter characteristics, and self-calibration modes. multi-channel - adcs are now available for data acquisition systems, and most users are well-educated with respect to the settling time requirements of the internal digital filter in these applications. references 1. w.l. lee and c.g. sodini, "a topology for higher-order interpolative coders," iscas proc . 1987. 2. p.f. ferguson, jr., a. ganesan and r. w. adams, "one-bit higher order sigma-delta a/d converters," iscas proc . 1990, vol. 2, pp. 890-893. 3. wai laing lee, a novel higher order interpolative modulator topology for high resolution oversampling a/d converters , mit masters thesis, june 1987. 4. r. w. adams, "design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques," j. audio engineering society , vol. 34, march 1986, pp. 153-166. 5. p. ferguson, jr., a. ganesan, r. adams, et. al., "an 18-bit 20-khz dual sigma-delta a/d converter," isscc digest of technical papers , february 1991. 6. robert adams, khiem nguyen, and karl sweetland, "a 113 db snr oversampling dac with segmented noise-shaped scrambling, " isscc digest of technical paper s , vol. 41, 1998, pp. 62, 63, 413. (describes a segmented audio dac with data scrambling). page 10 of 11
page 11 of 11 MT-023 7. robert w. adams and tom w. kwan, "data-directed sc rambler for multi-bit noise-shaping d/a converters," u.s. patent 5,404,142 , filed august 5, 1993, issued april 4, 1995. (describes a segmented audio dac with data scrambling). 8. y. matsuya, et. al., "a 16-bit oversampling a/d conversion technology using triple-integration noise shaping," ieee journal of solid-state circuits , vol. sc-22, no. 6, december 1987, pp. 921-929. 9. y. matsuya, et. al., "a 17-bit oversampling d/a conv ersion technology using multistage noise shaping," ieee journal of solid-state circuits , vol. 24, no. 4, august 1989, pp. 969-975. 10. paul h. gailus, william j. turney, and francis r. ye ster, jr., "method and arrangement for a sigma delta converter for bandpass signals," u.s. patent 4,857,928 , filed january 28, 1988, issued august 15, 1989. 11. s.a. jantzi, m. snelgrove, and p.f. ferguson jr., "a 4 th -order bandpass sigma-delta modulator," ieee journal of solid state circuits , vol. 38, no. 3, march 1993, pp. 282-291. 12. paul hendriks, richard schreier, joe dipilato, " high performance narrowband receiver design simplified by if digitizing subsystem in lqfp ," analog dialogue , vol. 35-3, june-july 2001. available at http://www.analog.com (describes an if subsystem with a bandpass sigma-delta adc having a nominal oversampling frequency of 18msps, a center frequency of 2.25mhz, and a bandwidth of 10khz - 150khz). 13. richard schreier, j. lloyd, l. singer, d. paterson, m. timko, m. hensley, g. patte rson, k behel, and j. zhou, "a 10-300 mhz if-digitizing ic with 90-105 db dynamic range and 15-333 khz bandwidth, ieee journal of solid state circuits , vol. 37, no. 12, , december 2002, pp. 1636-1644. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of customers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.

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